參數資料
型號： EP4SGX290NF45C2N
廠商： Altera
文件頁數： 9/82頁
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 290K 1932FBGA
產品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 3
系列： Stratix® IV GX
LAB/CLB數： 11648
邏輯元件/單元數： 291200
RAM 位總計： 17661952
輸入/輸出數： 920
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1932-BBGA
供應商設備封裝： 1932-FBGA（45x45）
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–9
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
The calibration accuracy for calibrated series and parallel OCTs are applicable at the
moment of calibration. When process, voltage, and temperature (PVT) conditions
change after calibration, the tolerance may change. Table 1–12 lists the Stratix IV OCT
without calibration resistance tolerance to PVT changes.
25-
R
S_left_shift
3.0, 2.5, 1.8, 1.5, 1.2
Internal left shift series
termination with calibration
(25-
R
S_left_shift setting)
VCCIO = 3.0, 2.5, 1.8,
1.5, 1.2 V
± 10
%
Notes to Table 1–11:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25-
R
S is not supported for 1.5 V and 1.2 V in Row I/O.
(3) 20-
R
S is not supported for 1.5 V and 1.2 V in Row I/O.
Table 1–11. OCT Calibration Accuracy Specifications for Stratix IV Devices (Part 2 of 2) (1)
Symbol
Description
Conditions
Calibration Accuracy
Unit
C2
C3,I3, M3
C4,I4
Table 1–12. OCT Without Calibration Resistance Tolerance Specifications for Stratix IV Devices
Symbol
Description
Conditions
Resistance Tolerance
Unit
C2
C3,I3, M3
C4,I4
25-
R
S
3.0 and 2.5
Internal series termination
without calibration (25-
setting)
VCCIO = 3.0 and 2.5 V
± 30
± 40
%
25-
R
S
1.8 and 1.5
Internal series termination
without calibration (25-
setting)
VCCIO = 1.8 and 1.5 V
± 30
± 40
%
25-
R
S
1.2
Internal series termination
without calibration (25-
setting)
VCCIO = 1.2 V
± 35
± 50
%
50-
R
S
3.0 and 2.5
Internal series termination
without calibration (50-
setting)
VCCIO = 3.0 and 2.5 V
± 30
± 40
%
50-
R
S
1.8 and 1.5
Internal series termination
without calibration (50-
setting)
VCCIO = 1.8 and 1.5 V
± 30
± 40
%
50-
R
S
1.2
Internal series termination
without calibration (50-
setting)
VCCIO = 1.2 V
± 35
± 50
%
100-
R
D
2.5
Internal differential
termination (100-
setting)
VCCIO = 2.5 V
± 25
%
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相關代理商/技術參數
參數描述
EP4SGX290NF45C3 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290NF45C3N 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290NF45C4 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290NF45C4N 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290NF45I3 功能描述:FPGA - 現場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 920 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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