參數(shù)資料
型號: EP4SGX290KF43C3
廠商: Altera
文件頁數(shù): 64/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 290K 1760FBGA
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 11648
邏輯元件/單元數(shù): 291200
RAM 位總計: 17661952
輸入/輸出數(shù): 880
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應商設備封裝: 1760-FCBGA
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–59
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–45 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to or higher than 1.25 Gbps.
Figure 1–6 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
When the data rate is equals to 800 Mbps, the LVDS soft-CDR/DPA sinusoidal jitter
tolerance allows up to 0.1 UI (125 ps) for jitter frequencies between 479.9 kHz and
20 MHz.
DLL and DQS Logic Block Specifications
Table 1–46 lists the DLL frequency range specifications for Stratix IV devices.
Table 1–45. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher
than 1.25 Gbps
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
F1
10,000
25.000
F2
17,565
25.000
F3
1,493,000
0.350
F4
50,000,000
0.350
Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
0.1 UI
P-P
baud/1667
20 MHz
Frequency
Sinusoidal Jitter Amplitude
20db/dec
Table 1–46. DLL Frequency Range Specifications for Stratix IV Devices (Part 1 of 2)
Frequency
Mode
Frequency Range (MHz)
Available Phase Shift
DQS Delay Buffer
Mode (1)
Number of
Delay
Chains
–2/–2×
Speed Grade
–3
Speed Grade
–4
Speed Grade
0
90-140
90-130
90-120
22.5°, 45°, 67.5°, 90°
Low
16
1
120-180
120-170
120-160
30°, 60°, 90°, 120°
Low
12
2
150-220
150-210
150-200
36°, 72°, 108°, 144°
Low
10
3
180-280
180-260
180-240
45°, 90°,135°, 180°
Low
8
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相關代理商/技術參數(shù)
參數(shù)描述
EP4SGX290KF43C3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290KF43C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290KF43C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290KF43I3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX290KF43I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 11648 LABs 880 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256