參數(shù)資料
型號(hào): EP4SGX230HF35I3N
廠商: Altera
文件頁數(shù): 44/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV FPGA 230K 1152FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 3
系列: Stratix® IV GX
LAB/CLB數(shù): 9120
邏輯元件/單元數(shù): 228000
RAM 位總計(jì): 17544192
輸入/輸出數(shù): 564
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–41
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
SDI Receiver Jitter Tolerance (12)
Sinusoidal jitter
tolerance (peak-to-peak)
Jitter Frequency =
15 KHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
> 2
UI
Jitter Frequency =
100 KHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
> 0.3
UI
Jitter Frequency =
148.5 MHz
Data Rate = 2.97 Gbps
(3G) Pattern = Single
Line Scramble Color Bar
> 0.3
UI
Sinusoidal jitter
tolerance (peak-to-peak)
Jitter Frequency =
20 KHz
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
> 1
UI
Jitter Frequency = 100
KHz Data Rate = 1.485
Gbps (HD) Pattern =
75% Color Bar
> 0.2
UI
Jitter Frequency = 148.5
MHz
Data Rate = 1.485 Gbps
(HD) Pattern = 75%
Color Bar
> 0.2
UI
SAS Transmit Jitter Generation (17)
Total jitter at 1.5 Gbps
(G1)
Pattern = CJPAT
0.55
0.55
0.55
UI
Deterministic jitter at
1.5 Gbps (G1)
Pattern = CJPAT
0.35
0.35
0.35
UI
Total jitter at 3.0 Gbps
(G2)
Pattern = CJPAT
0.55
0.55
0.55
UI
Deterministic jitter at
3.0 Gbps (G2)
Pattern = CJPAT
0.35
0.35
0.35
UI
Total jitter at 6.0 Gbps
(G3)
Pattern = CJPAT
0.25
0.25
0.25
UI
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1), (2) (Part 6 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
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