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參數(shù)資料
| 型號： | EP4SGX230FF35I4N |
| 廠商： | Altera |
| 文件頁數(shù)： | 26/82頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 230K 1152FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 3 |
| 系列： | Stratix® IV GX |
| LAB/CLB數(shù)： | 9120 |
| 邏輯元件/單元數(shù)： | 228000 |
| RAM 位總計(jì)： | 17544192 |
| 輸入/輸出數(shù)： | 564 |
| 電源電壓： | 0.87 V ~ 0.93 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1152-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1152-FBGA（27x27） |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–24
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Digital reset pulse
width
—
Minimum is two parallel clock cycles
—
Notes to Table 1–23:
(1) The
–2× speed grade is the fastest speed grade offered in the following Stratix IV GX devices: EP4SGX70DF29, EP4SGX110DF29,
EP4SGX110FF35, EP4SGX230DF29, EP4SGX110FF35, EP4SGX180DF29, EP4SGX230FF35, EP4SGX290FF35, EP4SGX180FF35,
EP4SGX290FH29, EP4SGX360FF35, and EPSGX360FH29.
(2) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK
rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(4) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(5) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum
reconfig_clk
frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more
information, refer to the Dynamic Reconfiguration in Stratix IV Devices chapter.
(6) The device cannot tolerate prolonged operation at this absolute maximum.
(7) You must use the 1.1-V RX VICM setting if the input serial data standard is LVDS.
(8) The rate matcher supports only up to
± 300 parts per million (ppm).
(9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–2 on page 1–33.
(10) Time for which the CDR must be kept in lock-to-reference (LTR) mode after rx_pll_locked goes high and before rx_locktodata is asserted
in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(12) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(13) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right
PLL Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(14) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(15) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the
link. You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about
clocking requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices
chapter.
(16) The Quartus II software automatically selects the appropriate /L divider depending on the configured data.
(17) The maximum transceiver-FPGA fabric interface speed of 265.625 MHz is allowed only in Basic low-latency PCS mode with a 32-bit interface
width. For more information, refer to the “Basic Double-Width Mode Configurations” section in the Transceiver Architecture in Stratix IV Devices
chapter.
(18) Figure 1–1 shows the AC gain curves for each of the 16 available equalization settings.
(19) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the
delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
(20) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to
derive the minimum eye opening requirement with Receiver Equalization enabled.
(21) The rise and fall time transition is specified from 20% to 80%.
(22) Stratix IV GX devices in -4 speed grade support Basic mode and deterministic latency mode transceiver configurations up to 6375 Mbps. These
configurations are shown in the figures 1-90, 1-92, 1-94, 1-96, and 1-101 in the Transceiver Architecture in Stratix IV Devices chapter.
(23) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 9 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP4SE230F29I4 | IC STRATIX IV FPGA 230K 780FBGA |
| EP4SE230F29C3 | IC STRATIX IV FPGA 230K 780FBGA |
| EP4SGX290FF35C4 | IC STRATIX IV FPGA 290K 1152FBGA |
| EP4SGX360FH29C4N | IC STRATIX IV FPGA 360K 780HBGA |
| EP4SGX180FF35I3N | IC STRATIX IV FPGA 180K 1152FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4SGX230HF35C2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX230HF35C2ES | 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1152FBGA |
| EP4SGX230HF35C2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4SGX230HF35C2NES | 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 1152FBGA 制造商:Altera Corporation 功能描述:IC FPGA 564 I/O 1152FBGA |
| EP4SGX230HF35C3 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 564 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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