參數(shù)資料
型號： EP4SGX230DF29C3NES
廠商： Altera
文件頁數(shù)： 57/82頁
文件大?。?/td> 0K
描述： IC STRATIX IV GX 230K 780-FBGA
標(biāo)準包裝： 1
系列： Stratix® IV GX
LAB/CLB數(shù)： 9120
邏輯元件/單元數(shù)： 228000
RAM 位總計： 17544192
輸入/輸出數(shù)： 372
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 780-BBGA
供應(yīng)商設(shè)備封裝： 780-FBGA（29x29）
配用： 544-2594-ND - KIT DEVELOPMENT STRATIX IV
544-2592-ND - KIT DEV STRATIX IV 4SGX230N/C2
1–52
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Configuration and JTAG Specifications
Table 1–37 lists the Stratix IV configuration mode specifications.
M144K
Block
Single-port
4K×36
0
1
475
440
380
400
350
MHz
Simple dual-port
2K×72
0
1
465
435
385
375
325
MHz
Simple dual-port
2K×72, with the
read-during-write
option set to Old
Data
0
1
260
240
205
225
200
MHz
Simple dual-port
2K×64 (with
ECC)
0
1
335
300
255
295
250
MHz
True dual-port
4K×36
0
1
400
375
330
350
310
MHz
True dual-port
4K×36, with the
read-during-write
option set to Old
Data
0
1
245
230
205
225
200
MHz
ROM 1 Port
0
1
540
500
435
450
420
MHz
ROM 2 Port
0
1
500
465
400
425
400
MHz
Min Pulse Width
(clock high time)
—
700
755
860
950
ps
Min Pulse Width
(clock low time)
—
500
625
690
ps
Notes to Table 1–36:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set
to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) This is only applicable to the Stratix IV E and GX devices.
(3) When you use the error detection CRC feature, there is no degradation in FMAX.
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices (1) (Part 2 of 2)
Memory
Mode
Resources Used
Performance
ALUTs
TriMatrix
Memory
–1 Industrial
and –2 /–2×
Commercial/
Industrial
Speed Grade
–3
Commercial/
Industrial/
Military
Speed Grade
–4
Commercial/
Industrial
Speed Grade
–3
Industrial/
Military
Speed
Grade
(2)
–4
Industrial
Speed
Grade
(2)
Unit
Table 1–37. Configuration Mode Specifications for Stratix IV Devices
Programming Mode
DCLK FMAX
Unit
Min
Typ
Max
Passive serial
—
125
MHz
Fast passive parallel (1)
——
125
MHz
Fast active serial
17
26
40
MHz
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參數(shù)描述
EP4SGX230DF29C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX230DF29C4ES 制造商:Altera Corporation 功能描述:IC FPGA 372 I/O 780FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 780FBGA
EP4SGX230DF29C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SGX230DF29C4NES 制造商:Altera Corporation 功能描述:IC STRATIX IV FPGA 制造商:Altera Corporation 功能描述:IC STRATIX IV GX FPGA 780FBGA
EP4SGX230DF29I3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV GX 9120 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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