參數(shù)資料
型號: EP4SE530H40C3NES
廠商: Altera
文件頁數(shù): 75/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV E 530K 1517-HBGA
標準包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計: 28033024
輸入/輸出數(shù): 976
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1517-BBGA 裸露焊盤
供應商設備封裝: 1517-HBGA(42.5x42.5)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–69
Glossary
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
November 2009
4.0
Added Table 1–9, Table 1–15, Table 1–38, and Table 1–39.
Added Figure 1–5 and Figure 1–6.
Added the “Transceiver Datapath PCS Latency” section.
Updated the “Electrical Characteristics”, “Operating Conditions”, and “I/O Timing”
sections.
All tables updated except Table 1–16, Table 1–24, Table 1–25, Table 1–26, Table 1–27,
Table 1–33, Table 1–34, and Table 1–45.
Updated Figure 1–2 and Figure 1–3.
Updated Equation 1–1.
Deleted Table 1-28, Table 1-29, Table 1-30, Table 1-42, Table 1-43, and Table 1-44.
Minor text edits.
June 2009
3.1
Added “Preliminary Specifications” to the footer of each page.
Updated Table 1–1, Table 1–2, Table 1–7, Table 1–10, Table 1–11, Table 1–12,
Table 1–21, Table 1–22, Table 1–23, Table 1–25, Table 1–37, Table 1–38, Table 1–39,
Table 1–40, and Table 1–44.
Minor text edits.
March 2009
3.0
Replaced Table 1–31 and Table 1–37.
Updated Table 1–1, Table 1–2, Table 1–5, Table 1–19, Table 1–41, Table 1–44,
Table 1–45, Table 1–49, and Table 1–51.
Added Table 1–21, Table 1–46, and Table 1–47
Added Figure 1–3.
Removed “Timing Model”, “Preliminary and Final Timing”, “I/O Timing Measurement
Methodology”, “I/O Default Capacitive Loading”, and “Referenced Documents” sections.
December 2008
2.1
Minor changes.
November 2008
2.0
Minor text edits.
Updated Table 1–19, Table 1–32, Table 1–34 - Table 1–39.
Minor text edits.
August 2008
1.1
Updated Table 1–1, Table 1–2, Table 1–4, Table 1–5, and Table 1–26.
Removed figures from “Transceiver Performance Specifications” on page 1–10 that are
repeated in the glossary.
Minor text edits and an additional note to Table 1–26.
May 2008
1.0
Initial release.
Table 1–55. Document Revision History (Part 3 of 3)
Date
Version
Changes
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參數(shù)描述
EP4SE530H40C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 21248 LABs 976 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE530H40C4ES 制造商:Altera Corporation 功能描述:IC FPGA 976 I/O 1517HBGA
EP4SE530H40C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 21248 LABs 976 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4SE530H40C4NES 制造商:Altera Corporation 功能描述:IC STRATIX IV E FPGA 1517HBGA 制造商:Altera Corporation 功能描述:IC FPGA 976 I/O 1517HBGA
EP4SE530H40I3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV E 21248 LABs 976 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256