參數(shù)資料
型號(hào): EP4SE530H35C3NES
廠商: Altera
文件頁數(shù): 20/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV E 530K 1152-HBGA
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 744
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1152-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 1152-HBGA(40x40)
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–19
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Differential and
common mode
return loss
PCIe (Gen 1
and Gen 2),
XAUI,
HiGig+,
CEI SR/LR,
Serial RapidIO
SR/LR,
CPRI LV/HV,
OBSAI,
SATA
Compliant
Programmable PPM
detector (8)
± 62.5, 100, 125, 200,
250, 300, 500, 1000
ppm
Run length
200
200
200
UI
Programmable
equalization (18)
——
16
16
16
dB
tLTR (9)
——
75
75
75
s
tLTR_LTD_Manual (10)
—15
15
15
s
tLTD_Manual (11)
4000
4000
4000
ns
tLTD_Auto (12)
4000
4000
4000
ns
Receiver CDR
3 dB Bandwidth in
lock-to-data (LTD)
mode
PCIe Gen1
20 - 35
MHz
PCIe Gen2
40 - 65
MHz
(OIF) CEI PHY
at 6.375 Gbps
20 - 35
MHz
XAUI
10 - 18
MHz
Serial RapidIO
1.25 Gbps
10 - 18
MHz
Serial RapidIO
2.5 Gbps
10 - 18
MHz
Serial RapidIO
3.125 Gbps
6 - 10
MHz
GIGE
6 - 10
MHz
SONET OC12
3 - 6
MHz
SONET OC48
14 - 19
MHz
Receiver buffer and
CDR offset
cancellation time
(per channel)
——
1850
0
——
1850
0
18500
recon
fig_
clk
cycles
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 4 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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