參數(shù)資料
| 型號： | EP4CGX75DF27I7N |
| 廠商： | Altera |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE IV GX FPGA 75K 672FBG |
| 產品培訓模塊： | Cyclone IV FPGA Family Overview |
| 特色產品： | Cyclone? IV FPGAs |
| 標準包裝： | 40 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB數(shù)： | 4620 |
| 邏輯元件/單元數(shù)： | 73920 |
| RAM 位總計： | 4257792 |
| 輸入/輸出數(shù)： | 310 |
| 電源電壓： | 1.16 V ~ 1.24 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 672-BGA |
| 供應商設備封裝： | 672-FBGA（27x27） |
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1–34
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
IOE Programmable Delay
Table 1–40 and Table 1–41 list the IOE programmable delay for Cyclone IV E 1.0 V
core voltage devices.
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
Parameter
Paths Affected
Number
of
Setting
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C8L
I8L
C8L
C9L
I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core
7
0
2.054
1.924
3.387
4.017
3.411
ns
Input delay from pin to
input register
Pad to I/O input
register
8
0
2.010
1.875
3.341
4.252
3.367
ns
Delay from output register
to output pin
I/O output
register to pad
2
0
0.641
0.631
1.111
1.377
1.124
ns
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network
12
0
0.971
0.931
1.684
2.298
1.684
ns
Notes to Table 1–40:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices (1), (2)
Parameter
Paths Affected
Number
of
Setting
Min
Offset
Max Offset
Unit
Fast Corner
Slow Corner
C8L
I8L
C8L
C9L
I8L
Input delay from pin to
internal cells
Pad to I/O
dataout to core
7
0
2.057
1.921
3.389
4.146
3.412
ns
Input delay from pin to
input register
Pad to I/O input
register
8
0
2.059
1.919
3.420
4.374
3.441
ns
Delay from output register
to output pin
I/O output
register to pad
2
0
0.670
0.623
1.160
1.420
1.168
ns
Input delay from
dual-purpose clock pin to
fan-out destinations
Pad to global
clock network
12
0
0.960
0.919
1.656
2.258
1.656
ns
Notes to Table 1–41:
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
相關PDF資料 |
PDF描述 |
|---|---|
| EP4CGX75DF27C6N | IC CYCLONE IV GX FPGA 75K 672FBG |
| EP4CE75F23I7N | IC CYCLONE IV FPGA 75K 484FBGA |
| M1AFS1500-2FG256 | IC FPGA 8MB FLASH 1.5M 256-FBGA |
| AFS1500-2FG256 | IC FPGA 8MB FLASH 1.5M 256-FBGA |
| AFS1500-2FGG256 | IC FPGA 8MB FLASH 1.5M 256-FBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4CGX75F17C8 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX75F23C8N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX75F23I7N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4-GD | 制造商:Box Enclosures & Assembly Services 功能描述:Enclosure End Plate |
| EP4-GR | 制造商:Box Enclosures & Assembly Services 功能描述:Enclosure End Plate |
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