參數(shù)資料
型號： EP4CGX75DF27C6N
廠商： Altera
文件頁數(shù)： 40/42頁
文件大?。?/td> 0K
描述： IC CYCLONE IV GX FPGA 75K 672FBG
產(chǎn)品培訓模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標準包裝： 40
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 4620
邏輯元件/單元數(shù)： 73920
RAM 位總計： 4257792
輸入/輸出數(shù)： 310
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BGA
供應商設備封裝： 672-FBGA（27x27）
Chapter 1: Cyclone IV Device Datasheet
1–7
Operating Conditions
December 2013
Altera Corporation
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone IV devices.
Supply Current
The device supply current requirement is the minimum current drawn from the
power supply pins that can be used as a reference for power size planning. Use the
Excel-based early power estimator (EPE) to get the supply current estimates for your
design because these currents vary greatly with the resources used. Table 1–6 lists the
I/O pin leakage current for Cyclone IV devices.
Bus Hold
The bus hold retains the last valid logic state after the source driving it either enters
the high impedance state or is removed. Each I/O pin has an option to enable bus
hold in user mode. Bus hold is always disabled in configuration mode.
Table 1–7 lists bus hold specifications for Cyclone IV devices.
Table 1–6. I/O Pin Leakage Current for Cyclone IV Devices (1), (2)
Symbol
Parameter
Conditions
Device
Min
Typ
Max
Unit
II
Input pin leakage current
VI = 0 V to VCCIOMAX
—
–10
—
10
A
IOZ
Tristated I/O pin leakage
current
VO = 0 V to VCCIOMAX
—
–10
—
10
A
Notes to Table 1–6:
(1) This value is specified for normal device operation. The value varies during device power
-up. This applies for all VCCIO settings (3.3, 3.0, 2.5,
1.8, 1.5, and 1.2 V).
(2) The 10
A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on.
Table 1–7. Bus Hold Parameter for Cyclone IV Devices (Part 1 of 2) (1)
Parameter
Condition
VCCIO (V)
Unit
1.2
1.5
1.8
2.5
3.0
3.3
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus hold
low,
sustaining
current
VIN > VIL
(maximum)
8
—
12
—
30—50—70
—
70
—
A
Bus hold
high,
sustaining
current
VIN < VIL
(minimum)
–8
—
–12
—
–30
—
–50
—
–70
—
–70
—
A
Bus hold
low,
overdrive
current
0 V < VIN < VCCIO
—
125
—
175
—
200
—
300
—
500
—
500
A
Bus hold
high,
overdrive
current
0 V < VIN < VCCIO
—
–125
—
–175
—
–200
—
–300
—
–500
—
–500
A
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相關代理商/技術參數(shù)
參數(shù)描述
EP4CGX75DF27C7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 4620 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX75DF27C7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 4620 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX75DF27C8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 4620 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX75DF27C8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 4620 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX75DF27I7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 4620 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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