參數(shù)資料
型號： EP4CGX50DF27C8N
廠商： Altera
文件頁數(shù)： 20/42頁
文件大?。?/td> 0K
描述： IC CYCLONE IV GX FPGA 50K 672FBG
產(chǎn)品培訓(xùn)模塊： Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 40
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 3118
邏輯元件/單元數(shù)： 49888
RAM 位總計(jì)： 2562048
輸入/輸出數(shù)： 310
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BGA
供應(yīng)商設(shè)備封裝： 672-FBGA（27x27）
Chapter 1: Cyclone IV Device Datasheet
1–27
Switching Characteristics
December 2013
Altera Corporation
Table 1–29 lists the active configuration mode specifications for Cyclone IV devices.
Table 1–30 lists the JTAG timing parameters and values for Cyclone IV devices.
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices
Programming Mode
DCLK Range
Typical DCLK
Unit
Active Parallel (AP) (1)
20 to 40
33
MHz
Active Serial (AS)
20 to 40
33
MHz
Note to Table 1–29:
(1) AP configuration mode is only supported for Cyclone IV E devices.
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices (1)
Symbol
Parameter
Min
Max
Unit
tJCP
TCK clock period
40
—
ns
tJCH
TCK clock high time
19
—
ns
tJCL
TCK clock low time
19
—
ns
tJPSU_TDI
JTAG port setup time for TDI
1
—
ns
tJPSU_TMS JTAG port setup time for TMS
3
—
ns
tJPH
JTAG port hold time
10
—
ns
tJPCO
JTAG port clock to output (2), (3)
—15
ns
tJPZX
JTAG port high impedance to valid output (2), (3)
—15
ns
tJPXZ
JTAG port valid output to high impedance (2), (3)
—15
ns
tJSSU
Capture register setup time
5
—
ns
tJSH
Capture register hold time
10
—
ns
tJSCO
Update register clock to output
—
25
ns
tJSZX
Update register high impedance to valid output
—
25
ns
tJSXZ
Update register valid output to high impedance
—
25
ns
Notes to Table 1–30:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–37.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
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EP4CGX50DF27I7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 3118 LABs 310 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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