參數(shù)資料
型號(hào): EP4CGX15BF14C7
廠商: Altera
文件頁(yè)數(shù): 26/42頁(yè)
文件大?。?/td> 0K
描述: IC CYCLONE IV FPGA 15K 169 FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 119
系列: CYCLONE® IV GX
LAB/CLB數(shù): 900
邏輯元件/單元數(shù): 14400
RAM 位總計(jì): 552960
輸入/輸出數(shù): 72
電源電壓: 1.16 V ~ 1.24 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 169-LBGA
供應(yīng)商設(shè)備封裝: 169-FBGA(14x14)
1–32
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
tDUTY
455545554555455545
55
%
TCCS
200
200
200
200
200
ps
Output jitter
(peak to peak)
500
500
550
600
700
ps
tLOCK (2)
1—
1
ms
Notes to Table 1–35:
(1) Cyclone IV E—emulated LVDS transmitter is supported at the output pin of all I/O Banks.
Cyclone IV GX—emulated LVDS transmitter is supported at the output pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–35. Emulated LVDS Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 2 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices (1), (3)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
fHSCLK (input
clock
frequency)
×10
10
437.5
10
370
10
320
10
320
10
250
MHz
×8
10
437.5
10
370
10
320
10
320
10
250
MHz
×7
10
437.5
10
370
10
320
10
320
10
250
MHz
×4
10
437.5
10
370
10
320
10
320
10
250
MHz
×2
10
437.5
10
370
10
320
10
320
10
250
MHz
×1
10
437.5
10
402.5
10
402.5
10
362
10
265
MHz
HSIODR
×10
100
875
100
740
100
640
100
640
100
500
Mbps
×8
80
875
80
740
80
640
80
640
80
500
Mbps
×7
70
875
70
740
70
640
70
640
70
500
Mbps
×4
40
875
40
740
40
640
40
640
40
500
Mbps
×2
20
875
20
740
20
640
20
640
20
500
Mbps
×1
10
437.5
10
402.5
10
402.5
10
362
10
265
Mbps
SW
400
400
400
550
640
ps
Input jitter
tolerance
500
500
550
600
700
ps
tLOCK (2)
—1—1—1—1—
1
ms
Notes to Table 1–36:
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
(2) tLOCK is the time required for the PLL to lock from the end-of-device configuration.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
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EP4CGX15BF14C7N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 900 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX15BF14C8 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 900 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX15BF14C8N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 900 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CGX15BF14I7 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone IV GX 900 LABs 72 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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