參數(shù)資料
型號： EP4CE40F23I7N
廠商： Altera
文件頁數(shù)： 38/42頁
文件大?。?/td> 0K
描述： IC CYCLONE IV FPGA 40K 484FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 60
系列： CYCLONE® IV E
LAB/CLB數(shù)： 2475
邏輯元件/單元數(shù)： 39600
RAM 位總計： 1161216
輸入/輸出數(shù)： 328
電源電壓： 1.15 V ~ 1.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FBGA（23x23）
Chapter 1: Cyclone IV Device Datasheet
1–5
Operating Conditions
December 2013
Altera Corporation
IDiode
Magnitude of DC current across
PCI-clamp diode when enable
——
—
10
mA
Notes to Table 1–3:
(1) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades.
(2) VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used)
and must be powered up and powered down at the same time.
(3) VCC must rise monotonically.
(4) VCCIO powers all input buffers.
(5) The I7 devices support extended operating junction temperature up to 125°C (usual range is –40°C to 100°C). When using I7 devices at the
extended junction temperature ranging from –40°C to 125°C, select C8 as the target device when designing in the Quartus II software. The I7
devices meet all C8 timing specifications when I7 devices operate beyond 100°C and up to 125°C.
(6) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range
within 50 ms.
(7) The POR time for Fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within
3ms.
Table 1–3. Recommended Operating Conditions for Cyclone IV E Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 1 of 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCCINT (3)
Core voltage, PCIe hard IP block, and
transceiver PCS power supply
—
1.16
1.2
1.24
V
VCCA (1), (3)
PLL analog power supply
—
2.375
2.5
2.625
V
VCCD_PLL (2)
PLL digital power supply
—
1.16
1.2
1.24
V
VCCIO (3), (4)
I/O banks power supply for 3.3
-V
operation
—
3.135
3.3
3.465
V
I/O banks power supply for 3.0
-V
operation
—
2.85
3
3.15
V
I/O banks power supply for 2.5
-V
operation
—
2.375
2.5
2.625
V
I/O banks power supply for 1.8
-V
operation
—
1.71
1.8
1.89
V
I/O banks power supply for 1.5
-V
operation
—
1.425
1.5
1.575
V
I/O banks power supply for 1.2
-V
operation
—
1.14
1.2
1.26
V
VCC_CLKIN
Differential clock input pins power
supply for 3.3
-V operation
—
3.135
3.3
3.465
V
Differential clock input pins power
supply for 3.0
-V operation
—
2.85
3
3.15
V
Differential clock input pins power
supply for 2.5
-V operation
—
2.375
2.5
2.625
V
Differential clock input pins power
supply for 1.8
-V operation
—
1.71
1.8
1.89
V
Differential clock input pins power
supply for 1.5
-V operation
—
1.425
1.5
1.575
V
Differential clock input pins power
supply for 1.2
-V operation
—
1.14
1.2
1.26
V
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