參數(shù)資料
型號： EP4CE15F23C9L
廠商： Altera
文件頁數(shù)： 18/42頁
文件大小： 0K
描述： IC CYCLONE IV FPGA 15K 484FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標準包裝： 60
系列： CYCLONE® IV E
LAB/CLB數(shù)： 963
邏輯元件/單元數(shù)： 15408
RAM 位總計： 516096
輸入/輸出數(shù)： 343
電源電壓： 0.97 V ~ 1.03 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FBGA（23x23）
Chapter 1: Cyclone IV Device Datasheet
1–25
Switching Characteristics
December 2013
Altera Corporation
tDLOCK
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset
is deasserted)
——
1
ms
tOUTJITTER_PERIOD_DEDCLK (6)
Dedicated clock output period jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_CCJ_DEDCLK (6)
Dedicated clock output cycle-to-cycle jitter
FOUT 100 MHz
—
300
ps
FOUT < 100 MHz
—
30
mUI
tOUTJITTER_PERIOD_IO (6)
Regular I/O period jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tOUTJITTER_CCJ_IO (6)
Regular I/O cycle-to-cycle jitter
FOUT 100 MHz
—
650
ps
FOUT < 100 MHz
—
75
mUI
tPLL_PSERR
Accuracy of PLL phase shift
—
±50
ps
tARESET
Minimum pulse width on areset signal.
10
—
ns
tCONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5 (7)
—
SCANCLK
cycles
fSCANCLK
scanclk
frequency
—
100
MHz
tCASC_OUTJITTER_PERIOD_DEDCLK
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
425
ps
Period jitter for dedicated clock output in cascaded
PLLs (FOUT 100 MHz)
—
42.5
mUI
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead.
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The VCO frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
■ Upstream PLL—0.59 MHz Upstream PLL bandwidth < 1 MHz
■ Downstream PLL—Downstream PLL bandwidth > 2 MHz
(9) PLL cascading is not supported for transceiver applications.
Table 1–25. PLL Specifications for Cyclone IV Devices (1), (2) (Part 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4CE15F23C9LN 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23I7 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23I7N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23I8L 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4CE15F23I8LN 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV E 963 LABs 343 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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