參數(shù)資料
型號: EP4CE10F17I7N
廠商: Altera
文件頁數(shù): 2/42頁
文件大小: 0K
描述: IC CYCLONE IV FPGA 10K 256FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 90
系列: CYCLONE® IV E
LAB/CLB數(shù): 645
邏輯元件/單元數(shù): 10320
RAM 位總計(jì): 423936
輸入/輸出數(shù): 179
電源電壓: 1.15 V ~ 1.25 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
1–10
Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
December 2013
Altera Corporation
Example 1–1 shows how to calculate the change of 50-I/O impedance from 25°C at
3.0 V to 85°C at 3.15 V.
Pin Capacitance
Table 1–11 lists the pin capacitance for Cyclone IV devices.
Example 1–1. Impedance Change
R
V = (3.15 – 3) × 1000 × –0.026 = –3.83
R
T = (85 – 25) × 0.262 = 15.72
Because
R
V is negative,
MFV = 1 / (3.83/100 + 1) = 0.963
Because
R
T is positive,
MFT = 15.72/100 + 1 = 1.157
MF = 0.963 × 1.157 = 1.114
Rfinal = 50 × 1.114 = 55.71
Table 1–11. Pin Capacitance for Cyclone IV Devices (1)
Symbol
Parameter
Typical –
Quad Flat
Pack
(QFP)
Typical –
Quad Flat
No Leads
(QFN)
Typical –
Ball-Grid
Array
(BGA)
Unit
CIOTB
Input capacitance on top and bottom I/O pins
7
6
pF
CIOLR
Input capacitance on right I/O pins
7
5
pF
CLVDSLR
Input capacitance on right I/O pins with dedicated LVDS output
8
7
pF
CVREFLR
Input capacitance on right dual
-purpose VREF pin when used as
VREF or user I/O pin
21
pF
CVREFTB
Input capacitance on top and bottom dual
-purpose VREF pin when
used as VREF or user I/O pin
23 (3)
23
pF
CCLKTB
Input capacitance on top and bottom dedicated clock input pins
7
6
pF
CCLKLR
Input capacitance on right dedicated clock input pins
6
5
pF
Notes to Table 1–11:
(1) The pin capacitance applies to FBGA, UBGA, and MBGA packages.
(2) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin
capacitance.
(3) CVREFTB for the EP4CE22 device is 30 pF.
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