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參數(shù)資料
| 型號(hào)： | EP2SGX90FF1508C5ES |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 1359/1486頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II GX 90K 1508-FBGA |
| 標(biāo)準(zhǔn)包裝： | 0 |
| 系列： | Stratix® II GX |
| LAB/CLB數(shù)： | 4548 |
| 邏輯元件/單元數(shù)： | 90960 |
| RAM 位總計(jì)： | 4520448 |
| 輸入/輸出數(shù)： | 650 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 1508-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1508-FBGA（30x30） |
| 配用： | 544-1725-ND - PCIE KIT W/S II GX EP2SGX90N 544-1724-ND - SI KIT W/SII GX EP2SGX90N 544-1702-ND - VIDEO KIT W/SII GX EP2SGX90N |
| 其它名稱(chēng)： | 544-1771 |
4–146
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
(OIF) CEI PHY Interface Mode
Table 4–53 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 4–53. MegaWizard Plug-In Manager Options (Page 9 for [OIF] CEI PHY Interface Mode)
ALT2GXB Setting
Description
Reference
What is the main PLL logical
reference clock index?
This option allows you to select the logical index for
the PLL that you intend to use with the current
configuration. This option is meaningful only if you
select the Use alternate Transmitter PLL and
Receiver PLL option on the Reconfig Alt PLL
page.
volume 2 of the Stratix II
GX Device Handbook.
How many input clocks?
This field allows you to select the number of
reference clock inputs needed to meet your CMU
PLL reconfiguration design goals. A maximum of
five input reference clocks are allowed.
volume 2 of the Stratix II
GX Device Handbook.
What is the selected input
clock source for the
Transmitter PLL and Receiver
PLL?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL,
this option allows you to select the clock source for
the current configuration.
volume 2 of the Stratix II
GX Device Handbook.
What is the selected input
clock source for the alternate
Transmitter PLL and Receiver
PLL?
If you select the Use alternate Transmitter PLL
and Receiver PLL option, you can select the clock
source for the alternate Transmitter PLL and the
Receiver PLL.
volume 2 of the Stratix II
GX Device Handbook.
What is the reconfig protocol
driven by clock 0….4?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL,
these options allow you to select the functional
mode for the respective reference clock source.
volume 2 of the Stratix II
GX Device Handbook.
What is the clock 0….4 input
frequency?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL,
these options allow you to select the reference
clock frequencies for each clock source.
volume 2 of the Stratix II
GX Device Handbook.
Use clock 1....4 reference
clock divider
If you select more than one input reference clock
source for the transmitter and/or receiver PLL,
these options allow you to instruct the
MegaWizard about the REFCLK pre-divider on
input reference clocks.
volume 2 of the Stratix II
GX Device Handbook.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2SGX90FF1508C5N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II GX 4548 LABs 650 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX90FF1508I4 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II GX 4548 LABs 650 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX90FF1508I4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Stratix II GX 4548 LABs 650 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2-SI | 制造商:Box Enclosures & Assembly Services 功能描述:END PLATE FOR SERIES 2, SILVER ANODIZED, 1.18 H X 4.27 W 制造商:Box Enclosures & Assembly Services 功能描述:Enclosure End Plate 制造商:Box Enclosures & Assembly Services 功能描述:END PLATE; Accessory Type:End Plate; For Use With:Extruded Aluminum Enclosures, BEX Series 2; Body Color:Silver; Body Material:Aluminum; External Height:1.18"; External Width:4.27"; Features:Silver; Leaded Process Compatible:Yes ;RoHS Compliant: Yes |
| EP3 | 制造商:Datak Corporation 功能描述: |
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