- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295887 > EP2SGX60EF1152C5 (ALTERA CORP) FPGA, 60440 CLBS, 640 MHz, PBGA1152 PDF資料下載
參數(shù)資料
| 型號： | EP2SGX60EF1152C5 |
| 廠商： | ALTERA CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 60440 CLBS, 640 MHz, PBGA1152 |
| 封裝： | MS-034AAR-1, FBGA-1152 |
| 文件頁數(shù)： | 30/768頁 |
| 文件大小： | 4252K |
| 代理商： | EP2SGX60EF1152C5 |
Altera Corporation
3–1
May 2007
3. Configuration & Testing
IEEE Std. 1149.1
JTAG Boundary-
Scan Support
All Stratix II devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus II software or hardware
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI,TMS and TRST pins have weak internal
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the VCCIO power supply of bank 4.
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap II embedded logic analyzer. Stratix II
devices support the JTAG instructions shown in Table 3–1.
1
Stratix II, Stratix, Cyclone II, and Cyclone devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
The Stratix II device instruction register length is 10 bits and the
USERCODE
register length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Stratix II devices.
SII51003-4.2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP2SGX60EF1152I4N | FPGA, 60440 CLBS, 717 MHz, PBGA1152 |
| EP2SGX60EF1152I4 | FPGA, 60440 CLBS, 717 MHz, PBGA1152 |
| EP2SGX60DF780I4N | FPGA, 60440 CLBS, 717 MHz, PBGA780 |
| EP2SGX60DF780C5 | FPGA, 60440 CLBS, 640 MHz, PBGA780 |
| EP2SGX60DF780C5N | FPGA, 60440 CLBS, 640 MHz, PBGA780 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2SGX60EF1152C5N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60EF1152I4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX60EF1152I4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix II GX 3022 LABs 534 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2SGX90 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Package Information Datasheet for Mature Altera Devices |
| EP2SGX90E | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Stratix II GX Device |
發(fā)布緊急采購，3分鐘左右您將得到回復。