
10–24
Altera Corporation
Stratix II GX Device Handbook, Volume 2
October 2007
Stratix II and Stratix II GX I/O Banks
Clock I/O Pins
The PLL clock I/O pins consist of clock inputs (INCLK), external feedback
inputs (FBIN), and external clock outputs (EXTCLK). Clock inputs are
located at the left and right I/O banks (banks 1, 2, 5, and 6) to support fast
PLLs, and at the top and bottom I/O banks (banks 3, 4, 7, and 8) to
support enhanced PLLs. Both external clock outputs and external
feedback inputs are located at enhanced PLL external clock output banks
(banks 9, 10, 11, and 12) to support enhanced PLLs.
Table 10–3 shows the
PLL clock I/O support in the I/O banks of Stratix II and Stratix II GX
devices.
Table 10–3. I/O Standards Supported for Stratix II and Stratix II GX PLL Pins
(Part 1 of 2)
Fast PLL
Input
Output
Input
INCLK
FBIN
EXTCLK
INCLK
LVTTL
v
LVCMOS
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
v
3.3-V PCI-X
v
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-18 Class I
v
SSTL-18 Class II
v
1.8-V HSTL Class I
v
1.8-V HSTL Class II
v
1.5-V HSTL Class I
v
1.5-V HSTL Class II
v
Differential SSTL-2 Class I
v
Differential SSTL-2 Class II
v
Differential SSTL-18 Class I
v
Differential SSTL-18 Class II
v