
Altera Corporation
13–53
October 2007
Stratix II GX Device Handbook, Volume 2
Configuring Stratix II & Stratix II GX Devices
f
For more information on configuring multiple Altera devices in the same
chapter in volume 2 of the Configuration Handbook.
PS Configuration Timing
Figure 13–20 shows the timing waveform for PS configuration when
using a MAX II device as an external host.
Figure 13–20. PS Configuration Timing Waveform
(1)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2)
Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
(3)
Upon power-up, before and during configuration, CONF_DONE is low.
(4)
DCLK
should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[0]
is available as a user I/O pin after configuration and the state of this pin depends on the dual-purpose pin
settings.
Table 13–15 defines the timing parameters for Stratix II and Stratix II GX
devices for PS configuration.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA
User I/O
INIT_DONE
Bit 0
Bit 1
Bit 2
Bit 3
Bit n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z
User Mode
(4)
Table 13–15. PS Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
Parameter
Min
Max
Units
tCF2CD
nCONFIG
low to CONF_DONE low
800
ns
tCF2ST0
nCONFIG
low to nSTATUS low
800
ns