Altera Corporation
3–29
January 2008
Stratix II Device Handbook, Volume 2
External Memory Interfaces in Stratix II and Stratix II GX Devices
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p
or PLL 6.
Figure 3–11. Simplified Diagram of the DQS Logic Block
(1)
All features of the DQS logic block are accessible from the altdqs megafunction in the Quartus II software. You
should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory interface.
(2)
The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p
or PLL 5. The input reference clock for the DQS phase-shift circuitry on the top side of the device
can come from CLK[7..4]p or PLL 6.
(3)
This register is one of the DQS IOE input registers.
DQ
EN
Update
Enab
le
Circuitr
y
6
DQS
Dela
y
Settings
from
the
DQS
Phase-
Shift
Circuitr
y
DQS
or
DQSn
Pin
Input
Ref
erence
Cloc
k
(2)
DQS
Dela
y
Chain
Bypass
Phase
Offset
Settings
6
NOT
Postamble
Circuitry
gated_dqs
control
DQS
bus
PRN
CLRN
Q
DFF
reset
EnableN
A
B
V
CC
DQS'
SCLR
(3)