
5–26
Altera Corporation
Stratix II Device Handbook, Volume 1
April 2011
Timing Model
Figure 5–6. Measurement Setup for tzx
Table 5–35 specifies the input timing measurement setup.
tZX, Tristate to Driving High
tZX, Tristate to Driving Low
1 M
Ω
Din
OE
Dout
1 M
Ω
Din
OE
Dout
OE
Disable
Enable
Dout
Din
tzh
VCCINT
“1”
VCCIO
OE
Disable
Enable
Dout
Din
VCCINT
“0”
tzl
VCCIO
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2)
Notes (1)–(4)
I/O Standard
Measurement Conditions
Measurement Point
VCCIO (V)
VREF (V)
Edge Rate (ns)
VMEAS (V)
LVTTL (5)
3.135
1.5675
LVCMOS (5)
3.135
1.5675
2.5 V (5)
2.375
1.1875
1.8 V (5)
1.710
0.855
1.5 V (5)
1.425
0.7125
PCI (6)
2.970
1.485
PCI-X (6)
2.970
1.485
SSTL-2 Class I
2.325
1.163
2.325
1.1625
SSTL-2 Class II
2.325
1.163
2.325
1.1625
SSTL-18 Class I
1.660
0.830
1.660
0.83
SSTL-18 Class II
1.660
0.830
1.660
0.83
1.8-V HSTL Class I
1.660
0.830
1.660
0.83