| 鍨嬭櫉(h脿o)锛� | EP2S30F672C3 | 
| 寤犲晢锛� | Altera | 
| 鏂囦欢闋佹暩(sh霉)锛� | 165/768闋� | 
| 鏂囦欢澶�?銆�?/td> | 0K | 
| 鎻忚堪锛� | IC STRATIX II FPGA 30K 672-FBGA | 
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Three Reasons to Use FPGA's in Industrial Designs | 
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 10 | 
| 绯诲垪锛� | Stratix® II | 
| LAB/CLB鏁�(sh霉)锛� | 1694 | 
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 33880 | 
| RAM 浣嶇附瑷�(j矛)锛� | 1369728 | 
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 500 | 
| 闆绘簮闆诲锛� | 1.15 V ~ 1.25 V | 
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 | 
| 宸ヤ綔婧害锛� | 0°C ~ 85°C | 
| 灏佽/澶栨锛� | 672-BBGA | 
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 672-BGA锛�27x27锛� | 
| 鍏跺畠鍚嶇ū锛� | 544-1895 EP2S30F672C3-ND | 

| 鐩搁棞(gu膩n)PDF璩囨枡 | PDF鎻忚堪 | 
|---|---|
| EP2AGX95DF25C5N | IC ARRIA II GX FPGA 95K 572FBGA | 
| EP1S20F484C5 | IC STRATIX FPGA 20K LE 484-FBGA | 
| 445705-4 | CONN D-SUB RCPT HSING 3C3 MIX | 
| ACC50DRXS-S734 | CONN EDGECARD 100PS DIP .100 SLD | 
| 204501-5 | CONN D-SUB PLUG HD 15P SER 90 | 
| 鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) | 鍙冩暩(sh霉)鎻忚堪 | 
|---|---|
| EP2S30F672C3N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 | 
| EP2S30F672C4 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 | 
| EP2S30F672C4N | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 | 
| EP2S30F672C5 | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 FPGA - Stratix II 1694 LABs 500 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 | 
| EP2S30F672C5AA | 鍒堕€犲晢:Altera Corporation 鍔熻兘鎻忚堪:FPGA Stratix | 
 
