2–66
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
PLLs & Clock Networks
c4
vv
v
c5
v
vvv
v
Enhanced PLL 11 outputs
c0
vv
v
c1
vv
v
c2
vv
v
c3
v
vvv
c4
vv
c5
vvv
v
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
(Part 2
of 2)
Top Side Global & Regional
Clock Network Connectivity
DLLCLK
CLK12
CLK13
CLK14
CLK15
RC
LK
24
RC
LK
25
RC
LK
26
RC
LK
27
RC
LK
28
RC
LK
29
RC
LK
30
RC
LK
31
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs
(Part 1 of 2)
Bottom Side Global &
Regional Clock Network
Connectivity
DLLCL
K
CLK
4
CLK
5
CLK
6
CLK
7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
Clock pins
CLK4p
vv
v
CLK5p
vv
v
CLK6p
vv
v
CLK7p
v
vvv
CLK4n
vvv
CLK5n
vv
v
CLK6n
vv
v
CLK7n
vvv
Drivers from internal logic
GCLKDRV0
v
GCLKDRV1
v
GCLKDRV2
v