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參數(shù)資料
| 型號(hào)： | EP2S130F1508C4 |
| 廠商： | Altera |
| 文件頁數(shù)： | 619/768頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX II FPGA 130K 1508-FBG |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 7 |
| 系列： | Stratix® II |
| LAB/CLB數(shù)： | 6627 |
| 邏輯元件/單元數(shù)： | 132540 |
| RAM 位總計(jì)： | 6747840 |
| 輸入/輸出數(shù)： | 1126 |
| 電源電壓： | 1.15 V ~ 1.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1508-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1508-FBGA（30x30） |
| 其它名稱： | 544-1460 |
7–104
Altera Corporation
Stratix II Device Handbook, Volume 2
January 2008
Device Configuration Pins
Table 7–23 describes the optional configuration pins. If these optional
configuration pins are not enabled in the Quartus II software, they are
available as general-purpose user I/O pins. Therefore, during
configuration, these pins function as user I/O pins and are tri-stated with
weak pull-up resistors.
Table 7–23. Optional Configuration Pins
Pin Name
User Mode
Pin Type
Description
CLKUSR
N/A if option is on.
I/O if option is off.
Input
Optional user-supplied clock input synchronizes the
initialization of one or more devices. This pin is
enabled by turning on the Enable user-supplied
start-up clock (CLKUSR) option in the Quartus II
software.
INIT_DONE
N/A if option is on.
I/O if option is off.
Output open-drain Status pin can be used to indicate when the device
has initialized and is in user mode. When nCONFIG is
low and during the beginning of configuration, the
INIT_DONE
pin is tri-stated and pulled high due to
an external 10-k
to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the
INIT_DONE
pin will go low. When initialization is
complete, the INIT_DONE pin will be released and
pulled high and the device enters user mode. Thus,
the monitoring circuitry must be able to detect a
low-to-high transition. This pin is enabled by turning
on the Enable INIT_DONE output option in the
Quartus II software.
DEV_OE
N/A if option is on.
I/O if option is off.
Input
Optional pin that allows the user to override all
tri-states on the device. When this pin is driven low, all
I/O pins are tri-stated; when this pin is driven high, all
I/O pins behave as programmed. This pin is enabled
by turning on the Enable device-wide output enable
(DEV_OE) option in the Quartus II software.
DEV_CLRn
N/A if option is on.
I/O if option is off.
Input
Optional pin that allows you to override all clears on
all device registers. When this pin is driven low, all
registers are cleared; when this pin is driven high, all
registers behave as programmed. This pin is enabled
by turning on the Enable device-wide reset
(DEV_CLRn) option in the Quartus II software.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2S130F1508C4N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 6627 LABs 1126 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1508C4RB | 制造商:Altera Corporation 功能描述:FPGA Stratix |
| EP2S130F1508C5 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 6627 LABs 1126 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1508C5N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 6627 LABs 1126 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2S130F1508C5RB | 制造商:Altera Corporation 功能描述:FPGA Stratix |
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