參數(shù)資料
型號(hào): EP2AGX65DF25C4N
廠商: Altera
文件頁(yè)數(shù): 85/90頁(yè)
文件大?。?/td> 0K
描述: IC ARRIA II GX FPGA 65K 572FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 5
系列: Arria II GX
LAB/CLB數(shù): 2530
邏輯元件/單元數(shù): 60214
RAM 位總計(jì): 5371904
輸入/輸出數(shù): 252
電源電壓: 0.87 V ~ 0.93 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 572-FBGA
供應(yīng)商設(shè)備封裝: 572-FBGA
其它名稱(chēng): 544-2709
1–78
Chapter 1: Device Datasheet for Arria II Devices
Document Revision History
December 2013
Altera Corporation
December 2010
4.0
Added Arria II GZ information.
Added Table 1–61 with Arria II GX information.
Updated Table 1–1, Table 1–2, Table 1–5, Table 1–6, Table 1–7, Table 1–11, Table 1–35,
Table 1–37, Table 1–40, Table 1–42, Table 1–44, Table 1–45, Table 1–57, Table 1–61, and
Table 1–63.
Updated Figure 1–5.
Updated for the Quartus II version 10.0 release.
Updated the first paragraph for searchability.
Minor text edits.
July 2010
3.0
Updated Table 1–1, Table 1–4, Table 1–16, Table 1–19, Table 1–21, Table 1–23,
Table 1–25, Table 1–26, Table 1–30, and Table 1–35
Added Table 1–27 and Table 1–29.
Added I3 speed grade information to Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Table 1–35.
Updated the “Operating Conditions” section.
Removed “Preliminary” from Table 1–19, Table 1–21, Table 1–22, Table 1–23,
Table 1–24, Table 1–25, Table 1–26, Table 1–28, Table 1–30, Table 1–32, Table 1–33,
Table 1–34, and Figure 1–4.
Minor text edits.
March 2010
2.3
Updated for the Quartus II version 9.1 SP2 release:
Updated Table 1–3, Table 1–7, Table 1–19, Table 1–21, Table 1–22, Table 1–24,
Table 1–25 and Table 1–33.
Updated “Recommended Operating Conditions” section.
Minor text edits.
February 2010
2.2
Updated Table 1–19.
February 2010
2.1
Updated for Arria II GX v9.1 SP1 release:
Updated Table 1–19, Table 1–23, Table 1–28, Table 1–30, and Table 1–33.
Added Figure 1–5.
Minor text edits.
November 2009
2.0
Updated for Arria II GX v9.1 release:
Updated Table 1–1, Table 1–4, Table 1–13, Table 1–14, Table 1–19, Table 1–15,
Table 1–22, Table 1–24, and Table 1–28.
Added Table 1–6 and Table 1–33.
Added “Bus Hold” on page 1–5.
Added “IOE Programmable Delay” section.
Minor text edit.
June 2009
1.2
Updated Table 1–1, Table 1–3, Table 1–7, Table 1–8, Table 1–18, Table 1–23, Table 1–25,
Table 1–26, Table 1–29, Table 1–30, Table 1–31, Table 1–32, and Table 1–33.
Added Table 1–32.
Updated Equation 1–1.
March 2009
1.1
Added “I/O Timing” section.
February 2009
1.0
Initial release.
Table 1–69. Document Revision History (Part 2 of 2)
Date
Version
Changes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2AGX65DF25C5 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C5N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX65DF25C6ES 制造商:Altera Corporation 功能描述:FPGA Arria
EP2AGX65DF25C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - Arria II GX 2530 LABs 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256