參數(shù)資料
型號: EP2AGX260FF35I3
廠商: Altera
文件頁數(shù): 52/90頁
文件大?。?/td> 0K
描述: IC ARRIA II GX 260K 1152FBGA
標(biāo)準(zhǔn)包裝: 3
系列: Arria II GX
LAB/CLB數(shù): 10260
邏輯元件/單元數(shù): 244188
RAM 位總計: 12038144
輸入/輸出數(shù): 612
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1152-BBGA
供應(yīng)商設(shè)備封裝: 1152-FBGA(27x27)
1–48
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Peak-to-peak jitter
Jitter frequency = 22.1 KHz
> 8.5
UI
Peak-to-peak jitter
Jitter frequency =
1.875 MHz
> 0.1
UI
Peak-to-peak jitter
Jitter frequency = 20 MHz
> 0.1
UI
PCIe Transmit Jitter Generation (8)
Total jitter at 2.5 Gbps (Gen1)—
x1, x4, and x8
Compliance pattern
0.25
0.25
UI
Total jitter at 5 Gbps (Gen2)—
x1, x4, and x8
Compliance pattern
0.25
UI
PCIe Receiver Jitter Tolerance (8)
Total jitter at 2.5 Gbps (Gen1)
Compliance pattern
> 0.6
UI
Total jitter at 5 Gbps (Gen2)
Compliance pattern
Not supported
UI
PCIe (Gen 1) Electrical Idle Detect Threshold
VRX-IDLE-DETDIFFp-p (9)
Compliance pattern
65
175
65
175
UI
SRIO Transmit Jitter Generation (10)
Deterministic jitter
(peak-to-peak)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
0.17
0.17
UI
Total jitter (peak-to-peak)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
0.35
0.35
UI
SRIO Receiver Jitter Tolerance (10)
Deterministic jitter tolerance
(peak-to-peak)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.37
UI
Combined deterministic and
random jitter tolerance (peak-to-
peak)
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.55
UI
Sinusoidal jitter tolerance (peak-
to-peak)
Jitter frequency = 22.1 KHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 8.5
UI
Jitter frequency = 1.875 MHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.1
UI
Jitter frequency = 20 MHz
Data rate = 1.25, 2.5, 3.125 Gbps
Pattern = CJPAT
> 0.1
UI
GIGE Transmit Jitter Generation (11)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
0.14
0.14
UI
Total jitter (peak-to-peak)
Pattern = CRPAT
0.279
0.279
UI
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 3 of 7)
Symbol/
Description
Conditions
–C3 and –I3
–C4 and –I4
Unit
Min
Typ
Max
Min
Typ
Max
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EP2AGX260FF35I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260FF35I5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX260FF35I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 10260 LABs 612 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX45CU17C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 1805 LABs 156 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256