參數(shù)資料
型號： EP2AGX125DF25I3
廠商： Altera
文件頁數(shù)： 72/90頁
文件大?。?/td> 0K
描述： IC ARRIA II GX FPGA 125K 572FBGA
標準包裝： 5
系列： Arria II GX
LAB/CLB數(shù)： 4964
邏輯元件/單元數(shù)： 118143
RAM 位總計： 8315904
輸入/輸出數(shù)： 260
電源電壓： 0.87 V ~ 0.93 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 572-FBGA
供應商設備封裝： 572-FBGA
1–66
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
December 2013
Altera Corporation
Table 1–55 lists DPA lock time specifications for Arria II GX and GZ devices.
tRISE & tFALL
True differential I/O
standards
—
200—
—200
ps
Emulated differential
I/O standards with
three external output
resistor networks
—
250—
—300
ps
Emulated differential
I/O standards with
one external output
resistor
—
500—
—500
ps
TCCS
True LVDS
—
100
—
100
ps
Emulated
LVDS_E_3R
—
250—
—250
ps
Receiver
True differential I/O
standards - fHSDRDPA
(data rate)
SERDES factor
J = 3 to 10
150
—
1250
150
—
1250
Mbps
fHSDR (data rate)
SERDES factor
J = 3 to 10
—
—
Mbps
SERDES factor J = 2,
uses DDR registers
—
—
Mbps
SERDES factor J = 1,
uses an SDR register
—
—
Mbps
DPA run length
DPA mode
—
10000
—
10000
UI
Soft-CDR PPM
tolerance
Soft-CDR mode
—
300
—
300
± PPM
Sampling Window
(SW)
Non-DPA mode
—
300
—
300
ps
Notes to Table 1–54:
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 3 of 3)
Symbol
Conditions
C3, I3
C4, I4
Unit
Min
Typ
Max
Min
Typ
Max
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相關代理商/技術參數(shù)
參數(shù)描述
EP2AGX125DF25I3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125DF25I5 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125DF25I5N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 260 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125EF29C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2AGX125EF29C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Arria II GX 4964 LABs 372 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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