參數(shù)資料
型號(hào): EP224PC-7
廠商: Altera Corporation
英文描述: Classic EPLDs
中文描述: 經(jīng)典EPLDs
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 265K
代理商: EP224PC-7
4
Altera Corporation
EP220 & EP224 Classic EPLDs
Macrocells
Each macrocell includes a product-term block with 8
feeding an
OR
gate. One product term is dedicated to the Output Enable
(
OE
) control of the tri-state buffer. The global logic array allows each
product term to connect to the true or complement of each input—36
inputs for the EP220, 44 inputs for the EP224—and I/O feedback signal.
See
Figure 2
.
AND
product terms
Figure 2. EP220 & EP224 Macrocell
Macrocells can be individually configured for registered or combinatorial
operation, providing a mixed-mode operation not available in fixed-
architecture PAL devices. When registered output is selected, feedback
from the register to the logic array bypasses the output buffer. When
combinatorial output is selected, feedback comes from the I/O pin
through the output buffer, and can be used for bidirectional I/O. Unlike
PAL and GAL devices, all eight outputs on the EP220 and EP224 allow a
combinatorial feedback signal from the I/O pin to feed the logic array.
Data is clocked into the macrocell’s D register on the rising edge of the
global Clock.
Feedback
Select
D
Q
CLK
Inversion
Control
Programmable
Register
Output Enable
Feedback to
Logic Array
Pin, I/O, and
Macrocell Feedback
相關(guān)PDF資料
PDF描述
EP2C20 SECTION IV. I/O STANDARDS
EP2C35 SECTION IV. I/O STANDARDS
EP2C5 SECTION IV. I/O STANDARDS
EP2C50 SECTION IV. I/O STANDARDS
EP2C70 SECTION IV. I/O STANDARDS
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