參數(shù)資料
型號(hào): EP220LC-7A
廠商: Altera Corporation
英文描述: Classic EPLDs
中文描述: 經(jīng)典EPLDs
文件頁數(shù): 14/16頁
文件大?。?/td> 265K
代理商: EP220LC-7A
14
Altera Corporation
EP220 & EP224 Classic EPLDs
AC Operating Conditions: -7 & -10 Speed Grades
Note (1)
Notes to tables:
(1)
Operating conditions: V
CC
= 5 V
±
5
%
, T
A
= 0
°
C to 70
°
C for commercial use.
(2)
Measured with three I/O outputs switching.
(3)
The
t
PZX
and
t
PXZ
parameters are measured at
±
0.5 V from steady-state voltage that is driven by the specified
output load. The
t
PXZ
parameter is measured with C
L
= 5 pF and with all eight outputs switching.
Combinatorial Mode
EP220-7
EP224-7
EP220-10
EP224-10
Symbol
Parameter
Min
Max
Min
Max
Units
t
PD1
t
PD2
t
PZX
t
PXZ
t
OSR
t
OSC
Input or I/O to non-registered output, inversion on,
Note (2)
7.5
10
ns
Input or I/O to non-registered output, inversion off,
Note (2)
8.5
10
ns
Input or I/O to output enable,
Note (3)
9
10
ns
Input or I/O to output disable,
Note (3)
9
10
ns
Register mode output-to-output skew
300
300
ps
Combinatorial mode output-to-output skew
400
400
ps
Synchronous Clock Mode
EP220-7
EP224-7
EP220-10
EP224-10
Symbol
Parameter
Min
Max
Min
Max
Units
f
MAX
f
CNT1
f
CNT2
t
SU1
t
H
t
CO1
t
CO2
t
CNT
t
CL
t
CH
t
CP
Maximum frequency (pipelined), no feedback,
Note (2)
100
62.5
MHz
Maximum counter frequency, external feedback,
Note (2)
74
58.8
MHz
Maximum counter frequency, internal feedback,
Note (2)
100
60.6
MHz
Input or I/O setup time to global clock
7
10
ns
Input or I/O hold time from global clock
0
0
ns
Global clock to output delay,
Note (2)
6.5
7
ns
Global clock to output delay through combinatorial macrocell
11
13
ns
Minimum global clock period,
Note (2)
10
16.5
ns
Clock low time
4
7
ns
Clock high time
4
7
ns
Clock period
10
16
ns
相關(guān)PDF資料
PDF描述
EP220LI-12 Classic EPLDs
EP220PC-10 Classic EPLDs
EP220PC-10A Classic EPLDs
EP220PC-12 Classic EPLDs
EP220PC-7 Classic EPLDs
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