- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4422 > EP20K60EBC356-1 (Altera)IC APEX 20KE FPGA 600K 356-BGA PDF資料下載
參數(shù)資料
| 型號： | EP20K60EBC356-1 |
| 廠商： | Altera |
| 文件頁數(shù)： | 31/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC APEX 20KE FPGA 600K 356-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB數(shù)： | 2560 |
| 邏輯元件/單元數(shù)： | 2560 |
| RAM 位總計： | 32768 |
| 輸入/輸出數(shù)： | 196 |
| 門數(shù)： | 162000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 356-BGA |
| 供應(yīng)商設(shè)備封裝： | 356-BGA（35x35） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁
20
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
The counter mode uses two three-input LUTs: one generates the counter
data, and the other generates the fast carry bit. A 2-to-1 multiplexer
provides synchronous loading, and another AND gate provides
synchronous clearing. If the cascade function is used by an LE in counter
mode, the synchronous clear or load overrides any signal carried on the
cascade chain. The synchronous clear overrides the synchronous load.
LEs in arithmetic mode can drive out registered and unregistered versions
of the LUT output.
Clear & Preset Logic Control
Logic for the register’s clear and preset signals is controlled by LAB-wide
signals. The LE directly supports an asynchronous clear function. The
Quartus II software Compiler can use a NOT-gate push-back technique to
emulate an asynchronous preset. Moreover, the Quartus II software
Compiler can use a programmable NOT-gate push-back technique to
emulate simultaneous preset and clear or asynchronous load. However,
this technique uses three additional LEs per register. All emulation is
performed automatically when the design is compiled. Registers that
emulate simultaneous preset and load will enter an unknown state upon
power-up or when the chip-wide reset is asserted.
In addition to the two clear and preset modes, APEX 20K devices provide
a chip-wide reset pin (DEV_CLRn) that resets all registers in the device.
Use of this pin is controlled through an option in the Quartus II software
that is set before compilation. The chip-wide reset overrides all other
control signals. Registers using an asynchronous preset are preset when
the chip-wide reset is asserted; this effect results from the inversion
technique used to implement the asynchronous preset.
FastTrack Interconnect
In the APEX 20K architecture, connections between LEs, ESBs, and I/O
pins are provided by the FastTrack Interconnect. The FastTrack
Interconnect is a series of continuous horizontal and vertical routing
channels that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect consists of row and column interconnect
channels that span the entire device. The row interconnect routes signals
throughout a row of MegaLAB structures; the column interconnect routes
signals throughout a column of MegaLAB structures. When using the row
and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE,
or ESB in a device. See Figure 9.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24C00T-I/MC | IC EEPROM 128BIT 400KHZ 8DFN |
| A54SX16-1TQ176I | IC FPGA SX 24K GATES 176-TQFP |
| XM2S-0911 | CONN HOOD DSUB 9POS KIT |
| AT24C01BY6-YH-T | IC EEPROM 1KBIT 1MHZ 8DFN |
| XM2S-1511 | CONN HOOD DSUB 15POS KIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K60EBC356-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EBC356-1X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K60EBC356-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K60EBC356-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K60EBC356-2X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 196 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。