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參數(shù)資料
| 型號(hào)： | EP20K400EQC240-1 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁(yè)數(shù)： | 57/65頁(yè) |
| 文件大?。?/td> | 781K |
| 代理商： | EP20K400EQC240-1 |
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82
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Notes:
(1)
This parameter is measured without use of the ClockLock or ClockBoost circuits.
(2)
This parameter is measured with use of the ClockLock or ClockBoost circuits.
Power
Consumption
Detailed power consumption information for APEX 20K devices will be
released as it is available.
Conguration &
Operation
The APEX 20K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The APEX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device operation
is called user mode.
Before and during device configuration all I/Os are pulled to VCCIO by a
built-in weak pull-up resistor.
Table 26. EP20K400 External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSUBIDIR (1)
1.2
1.5
1.8
ns
tINHBIDIR (1)
0.0
ns
tOUTCOBIDIR (1)
2.0
4.0
2.0
4.1
2.0
5.5
ns
tXZBIDIR (1)
4.9
5.8
6.9
ns
tZXBIDIR (1)
6.0
7.1
8.4
ns
tINSUBIDIR (2)
1.2
1.5
1.8
ns
tINHBIDIR (2)
0.0
ns
tOUTCOBIDIR (2)
0.5
3.0
0.5
3.1
0.5
4.5
ns
tXZBIDIR (2)
3.9
4.8
5.9
ns
tZXBIDIR (2)
5.0
6.1
7.4
ns
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| EP20K400EQI240-2 | LOADABLE PLD, PQFP240 |
| EP20K400EQI240-3 | LOADABLE PLD, PQFP240 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K400FC672-1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K400FC672-1X | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400FC672-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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