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參數(shù)資料
| 型號(hào)： | EP20K400 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數(shù)： | 47/117頁 |
| 文件大?。?/td> | 570K |
| 代理商： | EP20K400 |
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Altera Corporation
47
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices also support the MultiVolt I/O interface feature. The
APEX 20KE
VCCINT
pins must always be connected to a 1.8-V power
supply. With a 1.8-V V
CCINT
level, input pins are 1.8-V, 2.5-V, and 3.3-V
tolerant. The
VCCIO
pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V
power supply, depending on the I/O standard requirements. When the
VCCIO
pins are connected to a 1.8-V power supply, the output levels are
compatible with 1.8-V systems. When
VCCIO
pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
VCCIO
pins are connected to a 3.3-V power supply, the output high is
3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device
is 5.0-V tolerant with the addition of a resistor.
Table 13
summarizes APEX 20KE MultiVolt I/O support.
Notes to
Table 13
:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher than V
CCIO
, except for the 5.0-V
input case.
(2)
An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor. You also need a PCI
clamp and series resistor.
(3)
When V
CCIO
= 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs.
ClockLock &
ClockBoost
Features
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by sharing resources within the device. The ClockBoost
circuitry allows the designer to distribute a low-speed clock and multiply
that clock on-device. APEX 20K devices include a high-speed clock tree;
unlike ASICs, the user does not have to design and optimize the clock tree.
The ClockLock and ClockBoost features work in conjunction with the
APEX 20K device’s high-speed clock to provide significant improvements
in system performance and band-width. Devices with an X-suffix on the
ordering code include the ClockLock circuit.
APEX 20K devices support the ClockLock and ClockBoost clock
management features, which are implemented with PLLs. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
The ClockLock and ClockBoost features in APEX 20K devices are enabled
through the Quartus II software. External devices are not required to use
these features.
Table 13. APEX 20KE MultiVolt I/O Support
Note (1)
V
CCIO
(V)
Input Signals (V)
Output Signals (V)
1.8
v
v
v
2.5
v
v
v
3.3
v
v
v
5.0
1.8
v
2.5
3.3
5.0
1.8
2.5
3.3
v
(2)
v
(3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K400BC652-1 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400BC652-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K400BC652-1V | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP20K400BC652-1XV | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K400BC652-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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