參數(shù)資料
型號： EP20K30ETC144-3N
廠商： Altera
文件頁數(shù)： 57/117頁
文件大小： 0K
描述： IC APEX 20KE FPGA 300K 144-TQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 60
系列： APEX-20K®
LAB/CLB數(shù)： 120
邏輯元件/單元數(shù)： 1200
RAM 位總計： 24576
輸入/輸出數(shù)： 92
門數(shù)： 113000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應商設備封裝： 144-TQFP（20x20）
44
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Advanced I/O Standard Support
APEX 20KE IOEs support the following I/O standards: LVTTL,
LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS,
LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2
Class I and II.
f For more information on I/O standards supported by APEX 20KE
devices, see Application Note 117 (Using Selectable I/O Standards in Altera
Devices).
The APEX 20KE device contains eight I/O banks. In QFP packages, the
banks are linked to form four I/O banks. The I/O banks directly support
all standards except LVDS and LVPECL. All I/O banks can support LVDS
and LVPECL with the addition of external resistors. In addition, one block
within a bank contains circuitry to support high-speed True-LVDS and
LVPECL inputs, and another block within a particular bank supports
high-speed True-LVDS and LVPECL outputs. The LVDS blocks support
all of the I/O standards. Each I/O bank has its own VCCIO pins. A single
device can support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can
support a different standard independently. Each bank can also use a
separate VREF level so that each bank can support any of the terminated
standards (such as SSTL-3) independently. Within a bank, any one of the
terminated standards can be supported. EP20K300E and larger
APEX 20KE devices support the LVDS interface for data pins (smaller
devices support LVDS clock pins, but not data pins). All EP20K300E and
larger devices support the LVDS interface for data pins up to 155 Mbit per
channel; EP20K400E devices and larger with an X-suffix on the ordering
code add a serializer/deserializer circuit and PLL for higher-speed
support.
Each bank can support multiple standards with the same VCCIO for
output pins. Each bank can support one voltage-referenced I/O standard,
but it can support multiple I/O standards with the same VCCIO voltage
level. For example, when VCCIO is 3.3 V, a bank can support LVTTL,
LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
When the LVDS banks are not used as LVDS I/O banks, they support all
of the other I/O standards. Figure 29 shows the arrangement of the
APEX 20KE I/O banks.
相關PDF資料
PDF描述
3-338171-2 CONN PLUG 37POS R/A 30GOLD T/H
RMM36DTAD-S189 CONN EDGECARD 72POS R/A .156 SLD
LT3475EFE#PBF IC LED DRVR HP CONS CURR 20TSSOP
2-338168-2 CONN PLUG 9POS R/A 30GOLD T/H
RGM36DTAD-S189 CONN EDGECARD 72POS R/A .156 SLD
相關代理商/技術參數(shù)
參數(shù)描述
EP20K30ETI144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30ETI144-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K30ETI144-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EP20K400BC652-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*