參數(shù)資料
型號: EP20K200EFI672-2X
廠商: Altera
文件頁數(shù): 85/117頁
文件大小: 0K
描述: IC APEX 20KE FPGA 200K 672-FBGA
標準包裝: 40
系列: APEX-20K®
LAB/CLB數(shù): 832
邏輯元件/單元數(shù): 8320
RAM 位總計: 106496
輸入/輸出數(shù): 376
門數(shù): 404000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 672-BBGA
供應商設(shè)備封裝: 672-BGA(27x27)
Altera Corporation
7
APEX 20K Programmable Logic Device Family Data Sheet
Table 8. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
Full support
SignalTap logic analysis
Full support
32/64-Bit, 33-MHz PCI
Full compliance in -1, -2 speed
grades
Full compliance in -1, -2 speed grades
32/64-Bit, 66-MHz PCI
-
Full compliance in -1 speed grade
MultiVolt I/O
2.5-V or 3.3-V VCCIO
VCCIO selected for device
Certain devices are 5.0-V tolerant
1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO selected block-by-block
5.0-V tolerant with use of external resistor
ClockLock support
Clock delay reduction
2
× and 4× clock multiplication
Clock delay reduction
m /(n
× v) or m/(n × k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift
LVDS support
Up to four PLLs
ClockShift, clock phase adjustment
Dedicated clock and input pins Six
Eight
I/O standard support
2.5-V, 3.3-V, 5.0-V I/O
3.3-V PCI
Low-voltage complementary
metal-oxide semiconductor
(LVCMOS)
Low-voltage transistor-to-transistor
logic (LVTTL)
1.8-V, 2.5-V, 3.3-V, 5.0-V I/O
2.5-V I/O
3.3-V PCI and PCI-X
3.3-V Advanced Graphics Port (AGP)
Center tap terminated (CTT)
GTL+
LVCMOS
LVTTL
True-LVDS and LVPECL data pins
(in EP20K300E and larger devices)
LVDS and LVPECL signaling (in all BGA
and FineLine BGA devices)
LVDS and LVPECL data pins up to
156 Mbps (in -1 speed grade devices)
HSTL Class I
PCI-X
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
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