
Altera Corporation
53
APEX 20K Programmable Logic Device Family Data Sheet
Tables 17 and
18 summarize the ClockLock and ClockBoost parameters
for APEX 20KE devices.
Table 17. APEX 20KE ClockLock & ClockBoost Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
tINJITTER
Input jitter peak-to-peak
2
% of input
period
peak-to-
peak
tOUTJITTER Jitter on ClockLock or ClockBoost-
generated clock
0.35
% of
output period
RMS
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
45
55
%
Time required for ClockLock or
ClockBoost to acquire lock
40
s