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參數(shù)資料
| 型號(hào)： | EP20K200BC356-1ES |
| 英文描述： | 5V, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-CLCC |
| 中文描述： | FPGA的 |
| 文件頁(yè)數(shù)： | 38/114頁(yè) |
| 文件大?。?/td> | 1623K |
| 代理商： | EP20K200BC356-1ES |
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Altera Corporation
3
APEX 20K Programmable Logic Device Family Data Sheet
s
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLockTM feature reducing clock delay and skew
–
ClockBoostTM feature providing clock multiplication and
division
–
ClockShiftTM programmable clock phase and delay shifting
s
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
–
Bidirectional I/O performance (tCO + tSU) up to 250 MHz
–
LVDS performance up to 840 Mbits per channel
–
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
–
Programmable clamp to VCCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
–
Pull-up on I/O pins before and during configuration
s
Advanced interconnect structure
–
Four-level hierarchical FastTrack Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
s
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
–
FineLine BGATM packages maximize board space efficiency
s
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera QuartusTM II development system for
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| EP20K200CF484I8ES | ASIC |
| EP20K200CF484I9ES | ASIC |
| EP20K200CF672C7 | 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 28-CerDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP20K200BC356-1X | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 277 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200BC356-2 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 277 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200BC356-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K200BC356-3 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 832 Macro 277 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K200BC356-3ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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