參數(shù)資料
型號： EP20K160EQC240-2ES
英文描述： 5V, Byte Alterable E2PROM; Temperature Range: -55°C to 125°C; Package: 32-Extended LCC
中文描述： FPGA的
文件頁數(shù)： 29/114頁
文件大?。?/td> 1623K
代理商： EP20K160EQC240-2ES
Altera Corporation
21
APEX 20K Programmable Logic Device Family Data Sheet
Figure 9. APEX 20K Interconnect Structure
A row line can be driven directly by LEs, IOEs, or ESBs in that row.
Further, a column line can drive a row line, allowing an LE, IOE, or ESB to
drive elements in a different row via the column and row interconnect.
The row interconnect drives the MegaLAB interconnect to drive LEs,
IOEs, or ESBs in a particular MegaLAB structure.
A column line can be directly driven by LEs, IOEs, or ESBs in that column.
A column line on a device’s left or right edge can also be driven by row
IOEs. The column line is used to route signals from one row to another. A
column line can drive a row line; it can also drive the MegaLAB
interconnect directly, allowing faster connections between rows.
Figure 10 shows how the FastTrack Interconnect uses the local
interconnect to drive LEs within MegaLAB structures.
MegaLAB
I/O
MegaLAB
I/O
MegaLAB
I/O
Column
Interconnect
Column
Interconnect
Row
Interconnect
相關(guān)PDF資料
PDF描述
EP20K160EQC240-3ES 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack
EP20K160EQI208-1ES 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack T&R
EP20K160ERI208-3ES 5V, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-PLCC
EP20K160ERI240-1ES 5V, Byte Alterable EEPROM; Temperature Range: 0&degC to 70°C; Package: 32-PLCC
EP20K160ERI240-2ES 5V, Byte Alterable EEPROM; Temperature Range: 0&degC to 70°C; Package: 32-PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K160EQC240-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 175 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K160EQC240-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 175 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K160EQC240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K160EQC240-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 175 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K160EQI208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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