參數(shù)資料
型號： EP20K1500EFI1020-3ES
英文描述： 5V, Byte Alterable E2PROM; Temperature Range: -55°C to 125°C; Package: 32-CerDIP
中文描述： FPGA的
文件頁數(shù)： 13/114頁
文件大?。?/td> 1623K
代理商： EP20K1500EFI1020-3ES
Altera Corporation
11
APEX 20K Programmable Logic Device Family Data Sheet
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
To/From
Adjacent LAB,
ESB, or IOEs
To/From
Adjacent LAB,
ESB, or IOEs
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Local Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
Column
Interconnect
Row
Interconnect
MegaLAB Interconnect
相關(guān)PDF資料
PDF描述
EP20K160EBC356-1ES 5V, Byte Alterable E2PROM; Temperature Range: -55°C to 125°C; Package: 32-CerDIP
EP20K160EBC356-2ES 5V, Byte Alterable E2PROM; Temperature Range: -55°C to 125°C; Package: 32-CerDIP
EP20K160EBC356-3ES 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack
EP20K160EBI356-1ES 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack
EP20K160EBI356-2ES 5V, Byte Alterable E2PROM; Temperature Range: -40°C to 85°C; Package: 32-FlatPack
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K160E 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EP20K160EBC356-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 271 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K160EBC356-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K160EBC356-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 271 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K160EBC356-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 640 Macro 271 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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