參數(shù)資料
型號： EP20K1500CF1020C7
英文描述： ASIC
中文描述： 專用集成電路
文件頁數(shù)： 13/114頁
文件大小： 1623K
代理商： EP20K1500CF1020C7
Altera Corporation
11
APEX 20K Programmable Logic Device Family Data Sheet
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
Figure 3 shows the APEX 20K LAB.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
Figure 3. LAB Structure
To/From
Adjacent LAB,
ESB, or IOEs
To/From
Adjacent LAB,
ESB, or IOEs
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Local Interconnect
LEs drive local
MegaLAB, row,
and column
interconnects.
Column
Interconnect
Row
Interconnect
MegaLAB Interconnect
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K1500CF1020C8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K1500CF1020C9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K1500CF1020I7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K1500CF1020I8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EP20K1500CF1020I9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
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