VOL 3.3-V l" />
參數(shù)資料
型號: EP20K100QC240-3V
廠商: Altera
文件頁數(shù): 76/117頁
文件大?。?/td> 0K
描述: IC APEX 20K FPGA 100K 240-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計(jì): 53248
輸入/輸出數(shù): 189
門數(shù): 263000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 240-BFQFP
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
Altera Corporation
61
APEX 20K Programmable Logic Device Family Data Sheet
VOL
3.3-V low-level TTL output voltage IOL = 12 mA DC,
VCCIO =3.00 V (11)
0.45
V
3.3-V low-level CMOS output
voltage
IOL = 0.1 mA DC,
VCCIO =3.00 V (11)
0.2
V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC,
VCCIO = 3.00 to 3.60 V
0.1
× VCCIO
V
2.5-V low-level output voltage
IOL = 0.1 mA DC,
VCCIO =2.30 V (11)
0.2
V
IOL = 1 mA DC,
VCCIO =2.30 V (11)
0.4
V
IOL = 2 mA DC,
VCCIO =2.30 V (11)
0.7
V
II
Input pin leakage current
VI = 5.75 to –0.5 V
–10
10
A
IOZ
Tri-stated I/O pin leakage current
VO = 5.75 to –0.5 V
–10
10
A
ICC0
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade (12)
10
mA
VI = ground, no load, no
toggling inputs,
-2, -3 speed grades (12)
5mA
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (13)
20
50
W
VCCIO = 2.375 V (13)
30
80
W
Table 25. APEX 20K 5.0-V Tolerant Device DC Operating Conditions (Part 2 of 2)
Notes (2), (7), (8)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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