Notes to Figure 29: (1) For more i" />
參數(shù)資料
型號: EP20K100FC324-1V
廠商: Altera
文件頁數(shù): 58/117頁
文件大?。?/td> 0K
描述: IC APEX 20K FPGA 100K 208-PQFP
標準包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計: 53248
輸入/輸出數(shù): 252
門數(shù): 263000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BGA
供應商設備封裝: 324-FBGA(19x19)
Altera Corporation
45
APEX 20K Programmable Logic Device Family Data Sheet
Figure 29. APEX 20KE I/O Banks
Notes to Figure 29:
(1)
For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for
Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE
Devices).
(2)
If the LVDS input and output blocks are not used for LVDS, they can support all of
the I/O standards and can be used as input, output, or bidirectional pins with
VCCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20K and APEX 20KE devices can be used in a mixed-
voltage environment, they have been designed specifically to tolerate any
possible power-up sequence. Therefore, the VCCIO and VCCINT power
supplies may be powered in any order.
f For more information, please refer to the “Power Sequencing
Considerations” section in the Configuring APEX 20KE & APEX 20KC
Devices chapter of the Configuration Devices Handbook.
Signals can be driven into APEX 20K devices before and during power-up
without damaging the device. In addition, APEX 20K devices do not drive
out during power-up. Once operating conditions are reached and the
device is configured, APEX 20K and APEX 20KE devices operate as
specified by the user.
LVDS/LVPECL
Input
Block (2)
(1)
LVDS/LVPECL
Output
Block (2)
(1)
Regular I/O Blocks Support
LVTTL
LVCMOS
2.5 V
1.8 V
3.3 V PCI
LVPECL
HSTL Class I
GTL+
SSTL-2 Class I and II
SSTL-3 Class I and II
CTT
AGP
Individual
Power Bus
I/O Bank 8
I/O Bank 1
I/O Bank 2
I/O Bank 3
I/O Bank 4
I/O Bank 5
I/O Bank 6
I/O Bank 7
相關PDF資料
PDF描述
A1425A-PLG84I IC FPGA 2500 GATES 84-PLCC
ACB106DHHT-S578 EDGECARD 212POS .050 SLD W/POSTS
A1440A-1PL84I IC FPGA 4K GATES 84-PLCC
A14V40A-PL84C IC FPGA 4K GATES 3.3V 84-PLCC
ABB106DHHT-S578 EDGECARD 212POS .050 SLD W/POSTS
相關代理商/技術參數(shù)
參數(shù)描述
EP20K100FC324-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100FC324-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100FC324-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100FC324-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 252 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100FC324-2V 制造商:Rochester Electronics LLC 功能描述:- Bulk