參數(shù)資料
型號： EP20K100EQC208-1
廠商： Altera
文件頁數(shù)： 53/117頁
文件大小： 0K
描述： IC APEX 20KE FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 24
系列： APEX-20K®
LAB/CLB數(shù)： 416
邏輯元件/單元數(shù)： 4160
RAM 位總計： 53248
輸入/輸出數(shù)： 151
門數(shù)： 263000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
40
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices include an enhanced IOE, which drives the FastRow
interconnect. The FastRow interconnect connects a column I/O pin
directly to the LAB local interconnect within two MegaLAB structures.
This feature provides fast setup times for pins that drive high fan-outs
with complex logic, such as PCI designs. For fast bidirectional I/O timing,
LE registers using local routing can improve setup times and OE timing.
The APEX 20KE IOE also includes direct support for open-drain
operation, giving faster clock-to-output for open-drain signals. Some
programmable delays in the APEX 20KE IOE offer multiple levels of delay
to fine-tune setup and hold time requirements. The Quartus II software
compiler can set these delays automatically to minimize setup time while
providing a zero hold time.
Table 11 describes the APEX 20KE programmable delays and their logic
options in the Quartus II software.
The register in the APEX 20KE IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, an asynchronous preset can control the register. Figure 26
shows how fast bidirectional I/O pins are implemented in APEX 20KE
devices. This feature is useful for cases where the APEX 20KE device
controls an active-low input or another device; it prevents inadvertent
activation of the input upon power-up.
Table 11. APEX 20KE Programmable Delay Chains
Programmable Delays
Quartus II Logic Option
Input Pin to Core Delay
Decrease input delay to internal cells
Input Pin to Input Register Delay
Decrease input delay to input registers
Core to Output Register Delay
Decrease input delay to output register
Output Register tCO Delay
Increase delay to output pin
Clock Enable Delay
Increase clock enable delay
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參數(shù)描述
EP20K100EQC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EQC208-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EQC208-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EQC208-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EQC208-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 151 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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