Notes to Tables 17 and 18: (1) All input clock specifications must b" />
參數(shù)資料
型號： EP20K100EFC324-2
廠商： Altera
文件頁數(shù)： 68/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 100K 324-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 84
系列： APEX-20K®
LAB/CLB數(shù)： 416
邏輯元件/單元數(shù)： 4160
RAM 位總計(jì)： 53248
輸入/輸出數(shù)： 246
門數(shù)： 263000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 324-BGA
供應(yīng)商設(shè)備封裝： 324-FBGA（19x19）
54
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Notes to Tables 17 and 18:
(1)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2)
The maximum lock time is 40 s or 2000 input clock cycles, whichever occurs first.
(3)
Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs are still
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
(4)
The PLL VCO operating range is 200 MHz fVCO 840 MHz for LVDS mode.
SignalTap
Embedded
Logic Analyzer
APEX 20K devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX 20K
device provides the ability to monitor design operation over a period of
time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
fIN
Input clock frequency
3.3-V LVTTL
1.5
290
1.5
257
MHz
2.5-V LVTTL
1.5
281
1.5
250
MHz
1.8-V LVTTL
1.5
272
1.5
243
MHz
GTL+
1.5
303
1.5
261
MHz
SSTL-2 Class
I
1.5
291
1.5
253
MHz
SSTL-2 Class
II
1.5
291
1.5
253
MHz
SSTL-3 Class
I
1.5
300
1.5
260
MHz
SSTL-3 Class
II
1.5
300
1.5
260
MHz
LVDS
1.5
420
1.5
350
MHz
Table 18. APEX 20KE Clock Input & Output Parameters
(Part 2 of 2)
Note (1)
Symbol
Parameter
I/O Standard
-1X Speed Grade
-2X Speed Grade
Units
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100EFC324-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EFC324-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC324-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC3242XN 制造商:Altera Corporation 功能描述:FPGA APEX 20K Family 100K Gates 4160 Cells 250MHz CMOS Technology 1.8V 324-Pin FBGA
EP20K100EFC324-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 246 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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