參數(shù)資料
型號(hào)： EP20K100EBI356-2X
廠商： Altera
文件頁數(shù)： 34/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 100K 356-BGA
標(biāo)準(zhǔn)包裝： 24
系列： APEX-20K®
LAB/CLB數(shù)： 416
邏輯元件/單元數(shù)： 4160
RAM 位總計(jì)： 53248
輸入/輸出數(shù)： 246
門數(shù)： 263000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 356-BGA
供應(yīng)商設(shè)備封裝： 356-BGA（35x35）
Altera Corporation
23
APEX 20K Programmable Logic Device Family Data Sheet
Figure 11 shows the intersection of a row and column interconnect, and
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
APEX 20KE devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow interconnect, which routes signals directly into the local
interconnect without having to drive through the MegaLAB interconnect.
FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K300E
and larger devices, the FastRow interconnect drives the two MegaLABs in
the top left corner, the two MegaLABs in the top right corner, the two
MegaLABS in the bottom left corner, and the two MegaLABs in the
bottom right corner. On EP20K200E and smaller devices, FastRow
interconnect drives the two MegaLABs on the top and the two MegaLABs
on the bottom of the device. On all devices, the FastRow interconnect
drives all local interconnect in the appropriate MegaLABs except the local
interconnect on the side of the MegaLAB opposite the ESB. Pins using the
FastRow interconnect achieve a faster set-up time, as the signal does not
need to use a MegaLAB interconnect line to reach the destination LE.
Figure 12 shows the FastRow interconnect.
Row Interconnect
MegaLAB Interconnect
LE
Column
Interconnect
Local
Interconnect
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100EBI356-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EFC144-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100EFC144-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100EFC144-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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