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參數(shù)資料
| 型號(hào)： | EP20K100BC484-1 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PBGA484 |
| 文件頁(yè)數(shù)： | 3/68頁(yè) |
| 文件大?。?/td> | 975K |
| 代理商： | EP20K100BC484-1 |
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11
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
5.
AVR CPU Core
5.1
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2
Architectural Overview
Figure 5-1.
Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct
Addressing
Indirect
Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100BC484-2 | LOADABLE PLD, PBGA484 |
| EP20K100BC484-3 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-1 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-2 | LOADABLE PLD, PBGA484 |
| EP20K100BI484-3 | LOADABLE PLD, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| EP20K100BI356-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100BI356-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100BI356-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP20K100BI356-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100BI356-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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