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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 39. ESB Synchronous Timing Waveforms
Figure 40 shows the timing model for bidirectional I/O pin timing.
WE
CLK
ESB Synchronous Read
a0
d2
tESBDATASU
tESBARC
tESBDATACO2
a1
a2
a3
d1
tESBDATAH
a0
WE
CLK
dout0
din1
din2
din3
din2
tESBWESU
tESBSWC
tESBWEH
tESBDATACO1
a1
a2
a3
a2
din3
din2
din1
tESBDATAH
tESBDATASU
ESB Synchronous Write (ESB Output Registers Used)
dout1
Rdaddress
Data-Out
Wraddress
Data-Out
Data-In