參數(shù)資料
型號： EP20K100BC324-1
廠商： ALTERA CORP
元件分類： PLD
英文描述： LOADABLE PLD, PBGA324
文件頁數(shù)： 9/68頁
文件大?。?/td> 975K
代理商： EP20K100BC324-1
17
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
5.8.1
Interrupt Behavior
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding inter-
rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence..
Assembly Code Example
in
r16, SREG
; store SREG value
cli
; disable interrupts during timed sequence
sbi
EECR, EEMWE
; start EEPROM write
sbi
EECR, EEWE
out
SREG, r16
; restore SREG value (I-bit)
C Code Example
char
cSREG;
cSREG = SREG;
/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG;
/* restore SREG value (I-bit) */
相關(guān)PDF資料
PDF描述
EP20K100BC324-2 LOADABLE PLD, PBGA324
EP20K100BC324-3 LOADABLE PLD, PBGA324
EP20K100BI324-1 LOADABLE PLD, PBGA324
EP20K100BI324-2 LOADABLE PLD, PBGA324
EP20K100BI324-3 LOADABLE PLD, PBGA324
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參數(shù)描述
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EP20K100BC356-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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EP20K100BC356-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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