Altera Corporation
3–9
August 2005
Stratix GX Device Handbook, Volume 1
Source-Synchronous Signaling With DPA
Figure 3–7. PLL & Channel Layout in EP1SGX40 Devices
(1)
Corner PLLs do not support DPA.
(2)
Not all eight phases are used by the receiver channel or transmitter channel in
non-DPA mode.
(3)
The center PLLs can only clock 20 transceivers in either direction. Using Fast PLL2,
you can clock a total of 40 transceivers, 20 in each direction.
Fast
PLL 1
Fast
PLL 2
1 Receiver
1 Transmitter
1 Receiver
1 Transmitter
INCLK0
PLL (1)
CLKIN
PLL (1)
CLKIN
INCLK1
23 Rows
22 Rows
8
Eight-Phase
Clock
Eight-Phase
Clock
8