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參數(shù)資料
| 型號(hào)： | EP1SGX25DF1020I6ES |
| 廠商： | ALTERA CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, PBGA1020 |
| 封裝： | 33 X 33 MM, 1 MM PITCH, FBGA-1020 |
| 文件頁(yè)數(shù)： | 43/279頁(yè) |
| 文件大?。?/td> | 3671K |
| 代理商： | EP1SGX25DF1020I6ES |
Altera Corporation
4–71
February 2005
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
Figure 4–42. Regional Clocks
Fast Regional Clock Network
In EP1SGX25 and EP1SGX10 devices, there are two fast regional clock
networks,
FCLK[1..0], within each quadrant, fed by input pins (see
Figure 4–43). In EP1SGX40 devices, there are two fast regional clock
networks within each half-quadrant (see Figure 4–44). The
FCLK[1..0]
clocks can also be used for high fanout control signals, such as
asynchronous clears, presets, clock enables, or protocol control signals
such as
TRDY and IRDY for PCI. Dual-purpose FCLK pins drive the fast
clock networks. All devices have eight
FCLK pins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. The I/O
interconnect drives this signal.
RCLK[1..0]
RCLK[3..2]
RCLK[5..4]
RCLK[7..6]
RCLK[15..14]
RCLK[13..12]
RCLK[9..8]
RCLK[11..10]
CLK[15..12]
CLK[3..0]
CLK[7..4]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
Recovered Clocks, or PLLs within
that Quadrant
Transceiver
Clocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP1SGX25DF1020I6N | FPGA, PBGA1020 |
| EP1SGX25DF1020I7ES | FPGA, PBGA1020 |
| EP1SGX25DF1020I7N | FPGA, PBGA1020 |
| EP1SGX25DF672C5ES | FPGA, PBGA672 |
| EP1SGX25DF672C6ES | FPGA, PBGA672 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1SGX25DF672C5 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25DF672C5N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25DF672C6 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25DF672C6N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix I GX 2566 LABs 455 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1SGX25DF672C6NGA | 制造商:Altera Corporation 功能描述: |
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