
4–124
Altera Corporation
Stratix GX Device Handbook, Volume 1
February 2005
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Figure 4–72 shows the timing requirements for the JTAG signals.
Figure 4–72. Stratix GX JTAG Waveforms
Table 4–36 shows the JTAG timing parameters and values for Stratix GX
devices.
EP1SGX40
0000
0010 0000 0100 0101
000 0110 1110
1
(1)
The most significant bit (MSB) is at the left end of the string.
(2)
The IDCODE’s least significant bit (LSB) is always 1.
Table 4–35. 32-Bit Stratix GX Device IDCODE (Part 2 of 2)
Device
IDCODE (32 Bits) (1)
Version (4 Bits)
Part Number (16 Bits)
Manufacturer Identity
(11 Bits)
LSB (1 Bit) (2)
Table 4–36. Stratix GX JTAG Timing Parameters & Values (Part 1 of 2)
Symbol
Parameter
Min (ns) Max (ns)
tJCP
TCK
clock period
100
tJCH
TCK
clock high time
50
tJCL
TCK
clock low time
50
tJPSU
JTAG port setup time
20
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
tJSSU
tJSH
t
JSCO
tJSXZ