
4–120
Altera Corporation
Stratix GX Device Handbook, Volume 1
February 2005
I/O Structure
However, there is additional resistance present between the device ball
and the input of the receiver buffer, as shown in
Figure 4–71. This
resistance is because of package trace resistance (which can be calculated
as the resistance from the package ball to the pad) and the parasitic layout
metal routing resistance (which is shown between the pad and the
intersection of the on-chip termination and input buffer).
Figure 4–71. Differential Resistance of LVDS Differential Pin Pair (RD)
Table 4–31 defines the specification for internal termination resistance for
commercial devices.
MultiVolt I/O Interface
The Stratix GX architecture supports the MultiVolt I/O interface feature,
which allows Stratix GX devices in all packages to interface with systems
of different supply voltages.
The Stratix GX VCCINT pins must always be connected to a 1.5-V power
supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and
3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
LVDS
Input Buffer
Differential On-Chip
Termination Resistor
9.3
Ω
9.3
Ω
0.3
Ω
0.3
Ω
RD
Pad
Package Ball
Pad
Table 4–31. Differential On-Chip Termination
Symbol
Description
Conditions
Resistance
Unit
Min
Typ
Max
Internal differential termination for LVDS
110
135
165
Ω
100
135
170
Ω
(1)
Data measured over minimum conditions (Tj = 0 C, VCCIO +5%) and maximum conditions (Tj = 85 C,
VCCIO =–5%).
(2)
Data measured over minimum conditions (Tj = –40 C, VCCIO +5%) and maximum conditions (Tj = 100 C,
VCCIO =–5%).
(3)
LVDS data rate is supported for 840 Mbps using internal differential termination.